IT8502E View Datasheet(PDF) - ITE Tech. INC.
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Description
Manufacturer
IT8502E Datasheet PDF : 398 Pages
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Contents
7.5 General Purpose I/O Port (GPIO)............................................................................................... 192
7.5.1 Overview ....................................................................................................................... 192
7.5.2 Features ........................................................................................................................ 192
7.5.3 EC Interface Registers ................................................................................................... 192
7.5.3.1 General Control Register (GCR) ........................................................................ 193
7.5.3.2 General Control 1 Register (GCR1) ................................................................... 194
7.5.3.3 General Control 2 Register (GCR2) ................................................................... 194
7.5.3.4 General Control 3 Register (GCR3) ................................................................... 194
7.5.3.5 General Control 4 Register (GCR4) ................................................................... 195
7.5.3.6 Port Data Registers A-J (GPDRA-GPDRJ)......................................................... 195
7.5.3.7 Port Data Mirror Registers A-J (GPDMRA-GPDMRJ) ......................................... 196
7.5.3.8 Port Control n Registers (GPCRn, n = A0-I7) ..................................................... 196
7.5.3.9 Output Type Registers B/D/H (GPOTB/D/H) ...................................................... 197
7.5.4 Alternate Function Selection .......................................................................................... 198
7.5.5 Programming Guide....................................................................................................... 202
7.6 EC Clock and Power Management Controller (ECPM) ............................................................... 203
7.6.1 Overview ....................................................................................................................... 203
7.6.2 Features ........................................................................................................................ 203
7.6.3 EC Interface Registers ................................................................................................... 203
7.6.3.1 Clock Gating Control 1 Register (CGCTRL1R) ................................................... 204
7.6.3.2 Clock Gating Control 2 Register (CGCTRL2R) ................................................... 205
7.6.3.3 Clock Gating Control 3 Register (CGCTRL3R) ................................................... 205
7.6.3.4 PLL Control (PLLCTRL)..................................................................................... 206
7.6.3.5 Auto Clock Gating (AUTOCG)............................................................................ 206
7.6.3.6 PLL Frequency (PLLFREQR) ............................................................................ 208
7.7 SMBus Interface (SMB) ............................................................................................................. 209
7.7.1 Overview ....................................................................................................................... 209
7.7.2 Features ........................................................................................................................ 209
7.7.3 Functional Description ................................................................................................... 209
7.7.3.1 SMBus Master Interface .................................................................................... 209
7.7.3.2 SMBus Slave Interface ...................................................................................... 210
7.7.3.3 SMBus Porting Guide ........................................................................................ 211
7.7.3.4 SMBus Master Programming Guide ................................................................... 217
7.7.3.5 Description of SMCLK and SMDAT Line Control in Software Mode .................... 227
7.7.3.6 Description of SMBus Slave Interface Select...................................................... 227
7.7.3.7 SMBus Waveform.............................................................................................. 229
7.7.4 EC Interface Registers ................................................................................................... 231
7.7.4.1 Host Status Register (HOSTA)........................................................................... 232
7.7.4.2 Host Control Register (HOCTL) ......................................................................... 233
7.7.4.3 Host Command Register (HOCMD) ................................................................... 233
7.7.4.4 Transmit Slave Address Register (TRASLA) ...................................................... 234
7.7.4.5 Data 0 Register (D0REG) .................................................................................. 234
7.7.4.6 Data 1 Register (D1REG) .................................................................................. 234
7.7.4.7 Host Block Data Byte Register (HOBDB) ........................................................... 234
7.7.4.8 Packet Error Check Register (PECERC) ............................................................ 235
7.7.4.9 Receive Slave Address Register (RESLADR) .................................................... 235
7.7.4.10 Slave Data Register (SLDA) .............................................................................. 235
7.7.4.11 SMBus Pin Control Register (SMBPCTL)........................................................... 235
7.7.4.12 Slave Status Register (SLSTA) .......................................................................... 236
7.7.4.13 Slave Interrupt Control Register (SICR) ............................................................. 236
7.7.4.14 Notify Device Address Register (NDADR) .......................................................... 236
7.7.4.15 Notify Data Low Byte Register (NDLB)............................................................... 237
7.7.4.16 Notify Data High Byte Register (NDHB) ............................................................. 237
7.7.4.17 Host Control Register 2 (HOCTL2)..................................................................... 237
7.7.4.18 Slave Interface Select Register (SLVISELR) ...................................................... 237
7.7.4.19 4.7 µs Low Register (4P7USL) ........................................................................... 238
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IT8502E/F/G V0.7.7
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