IT8502E View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8502E

Embedded Controller

ITE Tech. INC. 

Contents

7.16.4.1 External GPIO Address Register (EADDR) ........................................................ 306

7.16.4.2 External GPIO Data Register (EDAT)................................................................. 306

7.16.4.3 External GPIO Control Register (ECNT)............................................................. 306

7.16.4.4 External GPIO Status Register (ESTS). ............................................................. 307

7.17 Battery-backed SRAM (BRAM) .................................................................................................. 308

7.17.1 Overview ....................................................................................................................... 308

7.17.2 Features ........................................................................................................................ 308

7.17.3 Functional Description ................................................................................................... 308

7.17.3.1 P80L.................................................................................................................. 308

7.17.4 Host Interface Registers................................................................................................. 309

7.17.5 EC Interface Registers ................................................................................................... 309

7.17.5.1 SRAM Byte n Registers (SBTn, n= 0-191).......................................................... 309

7.18 Serial Peripheral Interface (SSPI)............................................................................................... 311

7.18.1 Overview ....................................................................................................................... 311

7.18.2 Features ........................................................................................................................ 311

7.18.3 Functional Description ................................................................................................... 311

7.18.3.1 Data Transmissions ........................................................................................... 311

7.18.3.2 SPI Mode .......................................................................................................... 311

7.18.3.3 Blocking and Non-blocking mode ....................................................................... 313

7.18.4 Host Interface Registers................................................................................................. 313

7.18.5 EC Interface Registers ................................................................................................... 314

7.18.5.1 SPI Data Register (SPIDATA)............................................................................ 314

7.18.5.2 SPI Control Register 1 (SPICTRL1) ................................................................... 315

7.18.5.3 SPI Control Register 2 (SPICTRL2) ................................................................... 316

7.18.5.4 SPI Start and End Status Register (SPISTS)...................................................... 316

7.18.5.5 SPI Control Register 3 (SPICTRL3) ................................................................... 317

7.18.6 Programming Guide....................................................................................................... 318

7.19 Serial Port (UART) ..................................................................................................................... 320

7.19.1 Overview ....................................................................................................................... 320

7.19.2 Features ........................................................................................................................ 320

7.19.3 Functional Description ................................................................................................... 320

7.19.4 Host Interface Registers................................................................................................. 320

7.19.5 EC Interface Registers ................................................................................................... 321

7.19.5.1 Receiver Buffer Register (RBR) ......................................................................... 321

7.19.5.2 Transmitter Holding Register (THR) ................................................................... 321

7.19.5.3 Interrupt Enable Register (IER) .......................................................................... 322

7.19.5.4 Interrupt Identification Register (IIR)................................................................... 322

7.19.5.5 FIFO Control Register (FCR) ............................................................................. 324

7.19.5.6 Divisor Latch LSB (DLL) .................................................................................... 324

7.19.5.7 Divisor Latch MSB (DLM) .................................................................................. 324

7.19.5.8 Scratch Pad Register (SCR) .............................................................................. 325

7.19.5.9 Line Control Register (LCR)............................................................................... 326

7.19.5.10 Modem Control Register (MCR) ......................................................................... 327

7.19.5.11 Line Status Register (LSR) ................................................................................ 328

7.19.5.12 Modem Status Register (MSR) .......................................................................... 329

7.19.5.13 EC Serial Port Mode Register (ECSPMR) .......................................................... 329

7.19.6 Programming Guide....................................................................................................... 329

7.19.6.1 Programming Sequence .................................................................................... 330

7.19.7 Software Reset .............................................................................................................. 330

7.19.8 Clock Input Operation .................................................................................................... 330

7.19.9 FIFO Interrupt Mode Operation ...................................................................................... 330

7.19.10 High Speed Baud Rate Activation .................................................................................. 331

7.20 Debugger (DBGR) ..................................................................................................................... 332

7.20.1 Overview ....................................................................................................................... 332

7.20.2 Features ........................................................................................................................ 332

7.20.3 Functional Description ................................................................................................... 332

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IT8502E/F/G V0.7.7

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