DSP56362/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56362/D Datasheet PDF : 168 Pages
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Freescale Semiconductor, Inc.
Signal/Connection Descriptions
Clock and PLL
CLOCK AND PLL
Table 1-4 Clock and PLL Signals
Signal
Name
Type
State during
Reset
Signal Description
EXTAL
Input Input
External Clock Input—An external clock source must be
connected to EXTAL in order to supply the clock to the
internal clock generator and PLL.
This input cannot tolerate 5V.
Clock Output—CLKOUT provides an output clock
synchronized to the internal core clock phase.
CLKOUT Output Chip-driven
If the PLL is enabled and both the multiplication and division
factors equal one, then CLKOUT is also synchronized to
EXTAL.
PCAP
Input Input
PINIT/
NMI
Input Input
If the PLL is disabled, the CLKOUT frequency is half the
frequency of EXTAL. CLKOUT is not functional at
frequencies of 100 MHz and above.
PLL Capacitor—PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor terminal to
PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP may be tied to VCC, GND, or left
floating.
PLL Initial/Non maskable Interrupt—During assertion of
RESET, the value of PINIT/NMI is written into the PLL Enable
(PEN) bit of the PLL control register, determining whether the
PLL is enabled or disabled. After RESET deassertion and
during normal instruction processing, the PINIT/NMI Schmitt-
trigger input is a negative-edge-triggered non maskable
interrupt (NMI) request internally synchronized to CLKOUT.
PINIT/NMI cannot tolerate 5 V.
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.
MOTOROLA
DSP56362 Advance Information
1-5
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