DSP56362/D View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56362/D Datasheet PDF : 168 Pages
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Signal
Name
CAS
RD
WR
TA
Freescale Semiconductor, Inc.
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Table 1-7 External Bus Control Signals (Continued)
Type
State during
Reset
Signal Description
Output
Output
Output
Input
Tri-stated
Tri-stated
Tri-stated
Ignored Input
Column Address Strobe—When the DSP is the bus
master, CAS is an active-low output used by DRAM to
strobe the column address. Otherwise, if the bus
mastership enable (BME) bit in the DRAM control
register is cleared, the signal is tri-stated.
Read Enable—When the DSP is the bus master, RD is
an active-low output that is asserted to read external
memory on the data bus (D0–D23). Otherwise, RD is tri-
stated.
Write Enable—When the DSP is the bus master, WR is
an active-low output that is asserted to write external
memory on the data bus (D0–D23). Otherwise, the
signals are tri-stated.
Transfer Acknowledge—If the DSP56362 is the bus
master and there is no external bus activity, or the
DSP56362 is not the bus master, the TA input is ignored.
The TA input is a data transfer acknowledge (DTACK)
function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity)
may be added to the wait states inserted by the BCR by
keeping TA deasserted. In typical operation, TA is
deasserted at the start of a bus cycle, is asserted to
enable completion of the bus cycle, and is deasserted
before the next bus cycle. The current bus cycle
completes one clock period after TA is asserted
synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the bus control register
(BCR), whichever is longer. The BCR can be used to set
the minimum number of wait states in external bus
cycles.
In order to use the TA functionality, the BCR must be
programmed to at least one wait state. A zero wait state
access cannot be extended by TA deassertion,
otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the
setting of the TAS bit in the operating mode register
(OMR).
TA functionality may not be used while performing DRAM
type accesses, otherwise improper operation may result.
MOTOROLA
DSP56362 Advance Information
1-7
For More Information On This Product,
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