SSD1809T View Datasheet(PDF) - Solomon Systech
Part Name
Description
Manufacturer
SSD1809T Datasheet PDF : 27 Pages
| |||
PIN DESCRIPTIONS
P/S (Parallel / Serial Interface)
This pin is an input pin which is used to select parallel interface or
serial interface. Input High for parallel interface (6800 or 80) while input
Low for serial interface (SPI).
68/80
This pin is an input pin which is used to select 6800 interface or 80
interface. Input High for 6800 interface while input Low for 80 interface.
D/C (Data / Command)
This input pin acknowledges the LCD driver that the input at SDA/D 0-
D7 is data or command. Input High for data while input Low for com-
mand.
CE (Chip Enable)
This pin is an input pin. The chip is enabled when this pin is Low.
CLK/ WR / SCK
When 6800-series parallel interface is selected, this input pin is
named as CLK which is a clock. Data on SDA/D 0-D7 are latched at the
falling edge of CLK.
When 80-series parallel interface is selected, this input pin is named
as WR which is a clock in write cycle. It is low enable for write data/
command and data on SDA/D 0-D7 are latched at the rising edge of WR.
In read cycle, this pin should be High.
When SPI is selected, this input pin is named as SCK which is a
serial clock. Data on SDA /D 0 is latched at the falling edge of SCK.
RES (Reset)
An active Low pulse to this pin reset the internal status of the driver
(same as power on reset). The minimum pulse width is 1 µs to initiate
the reset process.
SDA / D 0-D7 (Data)
SDA/D o-D7 is a bi-directional bus and is used for data/command
transfer. If 6800-series or 80-series parallel interface is selected, D 0-D7
are connected directly to MCU for data transfer.
When SPI is selected, D 0 is named as SDA which is a serial input of
the driver. It receives data/command from MCU to driver and transfers
serially. Meanwhile, D1-D7 pins can be High or Low.
R/W / RD
When 6800-series parallel interface is selected, this input pin is
named as R/W, Input High will read the display data RAM or the internal
status (Busy/Idle) while input Low will write the display data RAM or the
internal setup registers.
When 80-series parallel interface is selected, this input pin is named
as RD and is a clock in read cycle. It is low enable for read data/com-
mand and data SDA/D 0-D7 are latched at the rising edge of RD. In write
cycle, this pin should be High.
When SPI is selected, this input pin can be High or Low.
OSC1 (Oscillator Input)
For internal oscillator mode, this is an input pin for the internal low
power RC oscillator circuit. In this mode, an external resistor of certain
value should be connected between the OSC1 and OSC2 pins for a
range of internal operating frequencies (refer to Figure 1). For external
oscillator mode, OSC1 should be left open.
OSC2 (Oscillator Output / External Oscillator Input)
For internal oscillator mode, this is an output for the internal low
power RC oscillator circuit. For external oscillator mode, OSC2 will be
an input pin for external clock and no external resistor is needed.
VL L 6 - VLL2
Group of voltage level pins for driving the LCD panel. They can either
be connected to external driving circuit for external bias supply or con-
nected internally to built-in divider circuit if internal divider is enable. For
internal Voltage Generator enabled, a 1.0 µF capacitor to AVSS is
required on each pin.
DUM1 - DUM4
If the internal bias voltage levels generator is enabled, a 1µF
capacitor to AV SS is required on each pin.
C1N and C1P, C 2N and C 2P, C 3N and C 3P
If internal Voltage Generator is enabled with 2X DC-DC converter, a
0.1µF capacitor is required to connect between C1N & C 1P.
If internal Voltage Generator is enabled with 3X/4X DC-DC con-
verter, a 0.1µF capacitor is required to connect between C1N & C 1P and
C3N & C 3P.
If internal Voltage Generator is enabled with 5X DC-DC converter, a
0.1µF capacitor is required to connect these three pair of pins.
C+ and C-
If internal divider circuit is enabled, a 1µF capacitor is required to
connect between these two pins.
VR and VF
This is a feedback path for the gain control (external contrast control)
of VLL2 to V LL6. For adjusting the LCD driving voltage, it requires a feed-
back resistor placed between V R and VF, a gain control resistor placed
between VF and AVSS, a 4.7µF capacitor placed between VR and
AV SS. (Refer to the Application Circuit)
COM0-COM64 (Row Drivers)
These lines provide the LCD row driving signals to the LCD panel.
COM64 also serves as the common driving signal in the icon mode.
Output is 0V during display off.
SEG0-SEG159 (Column Drivers)
These 160 pins provide LCD column driving signal to LCD panel.
Output is 0V during display off.
AVDD and AVSS
AV DD and AV SS are the positive supply and ground to all of the ana-
log circuit respectively.
VCC
For using the internal Voltage Generator, a 0.1µF capacitor from this
pin to AV SS is required. It can also be an external bias input pin if inter-
nal Voltage Generator is not used. Power is supplied to the LCD Driving
Level Selector and HV Buffer Cell with this pin. Normally, this pin is not
intended to be a power supply to other components.
DVDD and DVSS
Power is supplied to the digital control circuit and DC/DC converter of
the driver using these two pins. DVDD is power and DVSS is ground.
VDC
VDC is the power supply to the DC/DC converter of the driver.
Remark: In SSD1809T TAB package, VDC pin is connected to DVDD
and P/S pin & 68/80 pin are connected to AVDD. Only 6800-parallel
interface can be used and DVDD will be the supply of the DC/DC con-
verter in this package.
SOLOMON
REV 1.3 SSD1809
03/02
11
Share Link: 