SAF-C167CR-16RM View Datasheet(PDF) - Siemens AG

Part Name

Description

Manufacturer

SAF-C167CR-16RM

16-Bit CMOS Single-Chip Microcontrollers

Siemens AG 

C167CR-16RM 20Dec96@09:25h Intermediate Version

CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and reception of

CAN frames in accordance with the CAN specification V2.0 part B (active), ie. the on-chip CAN-

Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message object 15 may

be configured for Basic CAN functionality. Both modes provide separate masks for acceptance

filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard

a number of identifiers in Basic CAN mode. All message objects can be updated independent from

the other objects and are equipped for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The

CAN-Module uses two pins of Port 4 to interface to a bus transceiver.

Note: When the CAN interface is to be used the segment address output on Port 4 must be limited

to 4 bits, ie. A19...A16. This is necessary to enable the alternate function of the CAN

interface pins.

Parallel Ports

The C167CR-16RM provides up to 111 I/O lines which are organized into eight input/output ports

and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-

wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional

ports which are switched to high impedance state when configured as inputs. The output drivers of

five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via

control registers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the

special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input

threshold may be selected individually for each byte of the respective ports.

All port lines have programmable alternate input or output functions associated with them.

PORT0 and PORT1 may be used as address and data lines when accessing external memory,

while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where

segmentation is enabled to access more than 64 KBytes of memory.

Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM

units and/or with the outputs of the PWM module.

Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE

and the system clock output (CLKOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

All port lines that are not used for these alternate functions may be used as general purpose IO

lines.

Semiconductor Group

26

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