DSP56001 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56001 Datasheet PDF : 64 Pages
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DSP56001 Electrical Characteristics
AC Electrical Characteristics - Reset, Stop, Mode Select, and Interrupt Timing
(Continued)
NOTE
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is rec-
ommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode.
Num
Characteristics
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
17 Delay from IRQA, IRQB Assertion to
External Memory Access Address Out
Valid Caused by First Interrupt
Instruction Fetch
Instruction Execution
5 cyc+tch
9*cyc+tch
*
—
—
5 cyc+tch
9*cyc+tch
*
—
—
5 cyc+tch
9*cyc+tch
*
—
—
ns
ns
18 Delay from IRQA, IRQB Assertion to
General Purpose Transfer Output Valid 11+cyc
—
11 cyc
—
11 cyc
—
ns
Caused by First Interrupt Instruction
+tch
+*tch
+*tch
Execution
19 Delay from Address Output Valid
Caused by First Interrupt Instruction
Execution to Interrupt Request
Deassertion for Level Sensitive Fast
Interrupts
—
2 cyc+tcl+
—
2 cyc+tcl+
—
2 cyc+tcl+ ns
(c* yc WS)
(c* yc WS)
(c* yc WS)
-4*4
-3*4
-2*7
20 Delay from RD Assertion to Interrupt
Request Deassertion for Level
Sensitive Fast Interrupts
2 cyc+
2 cyc+
2 cyc+ ns
—
(cy*c WS)
—
(cy*c WS)
—
(cy*c WS)
-4*0
-3*1
-2*5
21 Delay from WR Assertion to WS=0
Interrupt Request Deassertion for
WS>0 Level Sensitive Fast Interrupts
—
2 cyc-40
—
2 cyc-31
—
2 cyc-25 ns
—
cy*c+tcl+
—
c*yc+tcl+
—
c*yc+tcl+ ns
(cyc WS)
-4*0
(cyc WS)
-3*1
(cyc WS)
-2*5
22 Delay from General-Purpose Output
Valid to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts
- If Second Interrupt Instruction is:
Single Cycle
Two Cycle
—
tcl-60
—
tcl-46
—
—
(2 cyc)+tcl
—
(2 cyc)+tcl
—
* -60
* -46
tcl-37
ns
(2 cyc)+tcl ns
* -37
MOTOROLA
12
DSP56001
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