DSP56001 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56001 Datasheet PDF : 64 Pages
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DSP56001 Electrical Characteristics
AC Electrical Characteristics - Host I/O Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
(see Host Figures 1 through 6)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tHSDL = Host Synchronization Delay Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications
Num
Characteristics
20.5 MHz
Min
Max
30 Host Synchronous Delay (see Note 1)
31 HEN/HACK Assertion Width
(see Note 2)
a.CVR, ICR, ISR Read (see Note 4)
b.Read
c.Write
32 HEN/HACK Deassertion Width
(see Note 2 and 5)
32a Minimum Cycle Time Between Two
HEN Assertion for Consecutive CVR,
ICR, and ISR Reads (see Note 2)
33 Host Data Input Setup Time Before
HEN/HACK Deassertion
34 Host Data Input Hold Time After HEN/
HACK Deassertion
35 HEN/HACK Assertion to Output Data
Active from High Impedance
36 HEN/HACK Assertion to Output Data
Valid (periodically sampled, and not
100% tested)
37 HEN/HACK Deassertion to Output
Data High Impedance
38 Output Data Hold Time After HEN/
HACK Deassertion
39 HR/W Low Setup Time Before HEN
Assertion
40 HR/W Low Hold Time After HEN
Deassertion
41 HR/W High Setup Time to HEN
Assertion
42 HR/W High Hold Time After HEN/
HACK Deassertion
43 HA0-HA2 Setup Time Before HEN
Assertion
44 HA0-HA2 Hold Time After HEN
Deassertion
45 DMA HACK Assertion to HREQ
Deassertion
(see Note 3)
tcl
cyc+60
50
25
25
2*cyc+60
5
5
0
—
—
5
0
5
0
5
0
5
5
cyc+tcl
—
—
—
—
—
—
—
—
50
35
—
—
—
—
—
—
—
60
27 MHz
Min
Max
tcl
cyc+tcl
cyc+46
—
39
—
19
—
19
—
2*cyc+46
—
4
—
4
—
0
—
—
39
—
27
4
—
0
—
4
—
0
—
4
—
0
—
4
—
4
46
33 MHz
Min
Max
tcl
cyc+tcl
Unit
ns
cyc+37
—
ns
31
—
ns
16
—
ns
16
—
ns
2*cyc+37
—
ns
4
—
ns
4
—
ns
0
—
ns
—
31
ns
—
22
ns
4
—
ns
0
—
ns
4
—
ns
0
—
ns
4
—
ns
0
—
ns
4
—
ns
4
49
ns
MOTOROLA
18
DSP56001
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