PEB20320 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

PEB20320

Multichannel Network Interface Controller for HDLC

Infineon Technologies 

PEB 20320

Introduction

Pin Definitions and Functions (cont’d)

Pin No.

Symbol

P-MQFP-160-1

76

BERR

74

B16

Input (I) Function

Output (O)

I

Bus Error (Intel and Motorola bus mode)

This active low signal informs the

MUNICH32 that a bus cycle error has

occurred. The MUNICH32 terminates the

bus cycle.

In case of an erroneous read cycle in the

control and configuration section an

‘Action Request Fail’ interrupt is generated

and the action is suspended. In case of an

erroneous read cycle in the transmit data

section the corresponding frame is

aborted and a FO interrupt is generated. In

all other cases of read or write cycles

terminated with an error condition no

further actions are performed by the

MUNICH32. Please see Chapter 2.2,

‘Microprocessor Interface’, first paragraph

and Figure 18.

As bus cycles are executed without time

limit this signal prevents a hang-up

situation of the MUNICH32.

I

Word Operation

Setting this bit to VDD causes the

MUNICH32 to perform 32-bit long word

accesses to the shared memory, setting it

to VSS causes the MUNICH32 to perform

16-bit word accesses on the data lines

D(15:0) only. In 16-bit word access mode

the data lines D(31:16) should be left

open.

This bit is not dynamic and should be set

to VDD in Intel parity mode.

User’s Manual

16

01.2000

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