UPD754304GS-XXX-T2 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD754304GS-XXX-T2

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

TABLE OF CONTENTS

CHAPTER 1 GENERAL ................................................................................................................

1

1.1 Functional Outline .........................................................................................................

2

1.2 Ordering Information .....................................................................................................

3

1.3 Differences among Subseries Products ....................................................................

4

1.4 Block Diagram ................................................................................................................

5

1.5 Pin Configuration (Top View) .......................................................................................

6

CHAPTER 2 PIN FUNCTION .......................................................................................................

9

2.1 Pin Functions of µPD754304 ........................................................................................

9

2.2 Pin Functions ................................................................................................................. 12

2.2.1 P00 to P03 (PORT0)

P10 to P13 (PORT1) ....................................................................................................... 12

2.2.2 P20 to P23 (PORT2)

P30 to P33 (PORT3)

P50 to P53 (PORT5)

P60 to P63 (PORT6) and P70 to P73 (PORT7) ............................................................ 12

2.2.3 P80, P81 (PORT8) ........................................................................................................... 13

2.2.4 TI0/TI1 .............................................................................................................................. 13

2.2.5 PTO0, PTO1 ..................................................................................................................... 13

2.2.6 PCL ................................................................................................................................... 13

2.2.7 SCK, SO/SB0, and SI ...................................................................................................... 14

2.2.8 INT4 .................................................................................................................................. 14

2.2.9 INT0 and INT1 ................................................................................................................. 14

2.2.10 INT2 .................................................................................................................................. 15

2.2.11 KR0 to KR3

KR4 to KR7 ...................................................................................................................... 15

2.2.12 X1 and X2 ........................................................................................................................ 15

2.2.13 RESET .............................................................................................................................. 16

2.2.14 VDD .................................................................................................................................... 16

2.2.15 VSS .................................................................................................................................... 16

2.2.16 IC (µPD754302, and 754304 only) ................................................................................. 16

2.2.17 VPP (µPD75P4308 only) ...................................................................................................

16

2.2.18 MD0 to MD3 (µPD75P4308 only) ................................................................................... 16

2.3 Pin Input/Output Circuits .............................................................................................. 17

2.4 Recommended Connections for Unused Pins .......................................................... 19

CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP ................................ 21

3.1 Bank Configuration of Data Memory and Addressing Mode .................................. 21

3.1.1 Bank configuration of data memory ................................................................................ 21

3.1.2 Addressing mode of data memory .................................................................................. 23

3.2 Bank Configuration of General-Purpose Registers .................................................. 36

3.3 Memory-Mapped I/O ...................................................................................................... 41

User’s Manual U10123EJ2V1UM00

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