MT48LC128M4A2A2TG-75 View Datasheet(PDF) - Micron Technology
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MT48LC128M4A2A2TG-75 Datasheet PDF : 55 Pages
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WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are provided
with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst. For the generic WRITE com-
mands used in the following illustrations, auto precharge
is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
command applies to the new command. An example is
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11, A12: x4
A0-A9, A11: x8
A0-A9: x16
A12: x4
A11, A12: x8
A9, A11, A12: x16
A10
COLUMN
ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BA0, BA, 1
BANK
ADDRESS
Figure 13
WRITE Command
ADVANCE
512Mb: x4, x8, x16
SDRAM
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 512Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.
T0
T1
T2
T3
CLK
COMMAND WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
DIN
n
DIN
n+1
NOTE B t l th 2 DQM i LOW
Figure 14
WRITE Burst
T0
T1
T2
CLK
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
DIN
b
NOTE: DQM is LOW. Each WRITE
command may be to any bank.
DON’T CARE
Figure 15
WRITE to WRITE
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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