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STM8S103C2P6 View Datasheet(PDF) - STMicroelectronics

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Description
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STM8S103C2P6 Datasheet PDF : 56 Pages
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STM8S103xx, STM8S105xx
Figure 4. Flash memory organisation (STM8S103)
Up to
8 Kbytes
Flash
program
memory
UBC area
Remains write protected during IAP
Program memory area
Write access possible for IAP
Product overview
Programmable area from 128 bytes
(2 first pages) up to 8 Kbytes
(1 page steps)
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory in debug
mode. Once the read-out protection is activated, any attempt to toggle its status triggers a
global erase of the program and data memory. Even if no protection can be considered as
totally unbreakable, the feature provides a very high level of protection for a general purpose
microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: 4 different clock sources can be used to drive the master clock:
– 1-16 MHz High Speed External crystal (HSE)
– Up to 16 MHz High Speed user-external clock (HSE user-ext)
– 16 MHz High Speed Internal RC oscillator (HSI)
– 128 kHz Low Speed Internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
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