45PE80 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
45PE80 Datasheet PDF : 44 Pages
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75MHz, Serial Peripheral Interface Flash Memory
Operating Features Overview
Polling During a WRITE, PROGRAM, or ERASE Cycle
The following commands can be completed faster by not waiting for the worst-case de-
lay (tW, tPP, tPE, tBE, or tSE).
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE, PROGRAM, or ERASE cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addi-
tional protection is provided by driving RESET# LOW during the power-on process, and
driving it HIGH only when VCC has reached the correct voltage level, VCC,min.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected and in the active power mode.
When S# is HIGH, the device is deselected, but could remain in the active power mode
until all internal cycles have completed (PROGRAM, ERASE, WRITE). The device then
goes in to the standby power mode, and power consumption drops to ICC1.
The deep power-down mode is entered when the DEEP POWER-DOWN command is
executed. The device power consumption drops further to ICC2. The device remains in
this mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While
in the deep power-down mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see the DEEP POWER-DOWN section.
Status Register
The status register contains a number of status bits that can be read by the READ STA-
TUS REGISTER (RDSR) command. For a detailed description of the status register bits,
see the READ STATUS REGISTER section.
Protection Modes
Nonvolatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power-on reset and an internal timer (tPUW) can provide protection against inadver-
tent changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and ERASE commands are checked before they are accepted for ex-
ecution to ensure they consist of a number of clock pulses that is a multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events.
• Power-up
• Reset (RESET#) driven LOW
• WRITE DISABLE command completion
• PAGE WRITE command completion
• PAGE PROGRAM command completion
PDF: 09005aef845660e5
m45pe80.pdf - Rev. C 03/14 EN
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