MT29F8G16AJADAHCIT View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT29F8G16AJADAHCIT

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Micron Technology 

Architecture

Micron Confidential and Proprietary

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Architecture

These devices use NAND Flash electrical and command interfaces. Data, commands,

and addresses are multiplexed onto the same pins and received by I/O control circuits.

The commands received at the I/O control circuits are latched by a command register

and are transferred to control logic circuits for generating internal signals to control de-

vice operations. The addresses are latched by an address register and sent to a row de-

coder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word

by word (x16), through a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operations

and is erased using block-based operations. During normal page operations, the data

and cache registers act as a single register. During cache operations, the data and cache

registers operate independently to increase data throughput. The status register reports

the status of die operations.

Figure 8: NAND Flash Die (LUN) Functional Block Diagram

VCC VSS

I/Ox

I/O

control

Address register

Status register

CE#

CLE

ALE

WE#

RE#

WP#

LOCK1

R/B#

Command register

Control

logic

Note: 1. The LOCK pin is used on the 1.8V device.

Column decode

NAND Flash

array

(2 planes)

Data register

Cache register

ECC

PDF: 09005aef83b25735

m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2009 Micron Technology, Inc. All rights reserved.

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