MT29F8G16AJADAHCIT View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT29F8G16AJADAHCIT Datasheet PDF : 132 Pages
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Micron Confidential and Proprietary
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Device and Array Organization
Figure 12: Array Organization – MT29F8G16 (x16)
Die 0
Die 1
Cache Register
1056 words
1056 words
1024
32
1024
32
1056 words
1024
32
1056 words
1024
32
I/O7
I/O0
Data Register
1024
32
1024
32
1024
32
1024
32
1 page = (1K + 32 words)
2048 blocks
per plane
4096 blocks
per die
1 block
1 block
1 block
1 block
1 block = (1K + 32) words x 64 pages
= (64K + 2K) words
1 plane = (128K + 4K) bytes x 2048 blocks
= 2112Mb
1 die = 2112Mb x 2 planes
= 4224Mb
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
4092, 4094)1
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
4093, 4095)
Plane 0: even-
numbered blocks
(4096, 4098, ...,
8188, 8190)
Plane 1: odd-
numbered blocks
(4097, 4099, ...,
8189, 8191)
1 device = 4224Mb x 2 die
= 8448Mb
Note: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.
Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
Table 5: Array Addressing – MT29F8G16 ( x16)
Cycle
First
Second
Third
Fourth
Fifth
I/O[15:8]
LOW
LOW
LOW
LOW
LOW
I/07
CA7
LOW
BA7
BA15
LOW
I/06
CA6
LOW
BA6
BA14
LOW
I/05
CA5
LOW
PA5
BA13
LOW
I/04
CA4
LOW
PA4
BA12
LOW
I/03
CA3
LOW
PA3
BA11
LOW
I/02
CA2
CA10
PA2
BA10
BA183
I/01
CA1
CA9
PA1
BA9
BA17
I/O0
CA0
CA8
PA0
PA8
BA16
Notes:
1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA10 = 1, then CA[9:5] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
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