MT29F8G16AJADAHCIT View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT29F8G16AJADAHCIT Datasheet PDF : 132 Pages
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Micron Confidential and Proprietary
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Device and Array Organization
Device and Array Organization
Figure 9: Array Organization – MT29F4G08 (x8)
Cache Register
Data Register
2048 blocks
per plane
4096 blocks
per device
2112 bytes
2112 bytes
2048
64
2048
64
2048
64
2048
64
1 block
1 block
Plane of
even-numbered blocks
(0, 2, 4, 6, ..., 4092, 4094)
Plane of
odd-numbered blocks
(1, 3, 5, 7, ..., 4093, 4095)
DQ7
DQ0
1 page
1 block
= (2K + 64 bytes)
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 plane = (128K + 4K) bytes x 2048 blocks
= 2112Mb
1 device = 2112Mb x 2 planes
= 4224Mb
Table 2: Array Addressing – MT29F4G08 (x8)
Cycle
First
Second
Third
Fourth
Fifth
I/07
CA7
LOW
BA7
BA15
LOW
I/06
CA6
LOW
BA6
BA14
LOW
I/05
CA5
LOW
PA5
BA13
LOW
I/04
CA4
LOW
PA4
BA12
LOW
I/03
CA3
CA11
PA3
BA11
LOW
I/02
CA2
CA10
PA2
BA10
LOW
I/01
CA1
CA9
PA1
BA9
BA17
I/00
CA0
CA8
PA0
BA8
BA16
Notes:
1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. BA6 controls plane selection.
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN
16
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© 2009 Micron Technology, Inc. All rights reserved.
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