56F8357 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F8357 Datasheet PDF : 160 Pages
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Freescale Semiconductor, Inc.
Table 2-2 56F8357 Signal and Package Information for the 160-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
RXD1
(GPIOD7)
TCK
TMS
TDI
TDO
TRST
50
Input
Input
Receive Data — SCI1 receive data input
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
137
Schmitt
Input,
Test Clock Input — This input pin provides a gated clock
Input
pulled low to synchronize the test logic and shift serial data to the
internally JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.
138
Schmitt
Input,
Test Mode Select Input — This input pin is used to
Input
pulled high sequence the JTAG TAP controller’s state machine. It is
internally sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.
139
Schmitt
Input,
Test Data Input — This input pin provides a serial input
Input
pulled high data stream to the JTAG/EOnCE port. It is sampled on the
internally rising edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.
140
Output
Tri-stated Test Data Output — This tri-stateable output pin provides
a serial output data stream from the JTAG/EOnCE port. It
is driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.
136
Schmitt
Input,
Test Reset — As an input, a low signal on this pin
Input
pulled high provides a reset signal to the JTAG TAP controller. To
internally ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE
module must not be reset. In this case, assert RESET, but
do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.
22
56F8357 Technical Data
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