56F8355 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
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56F8355 Datasheet PDF : 172 Pages
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Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name Pin No. Type
State
During
Reset
Signal Description
VSSA_ADC
OCR_DIS
95
Supply
71
Input
Input
ADC Analog Ground — This pin supplies an analog ground to
the ADC modules.
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator.
Tie this pin to VDD to disable the on-chip regulator.
VCAP1
VCAP2
VCAP3
VCAP4
VPP1
VPP2
CLKMODE
49
Supply
122
75
13
119
Input
5
79
Input
Supply
Input
This pin is intended to be a static DC signal from power-up to
shut down. Do no try to toggle this pin for power savings
during operation.
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order
to bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to VDD (regulator disabled),
these pins become VDD_CORE and should be connected to a
regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
VPP1 - VPP2 — These pins should be left unconnected as an open
circuit for normal functionality.
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
EXTAL
XTAL
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
74
Input
Input
External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by
an external clock source.
73
Input/ Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
56F8355 Technical Data, Rev. 17
20
Freescale Semiconductor
Preliminary
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