DSP56852VF120 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56852VF120 Datasheet PDF : 48 Pages
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No.
D5
Signal Name
RESET
Type
Input
Description
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial Chip Operating mode is
latched from the D[15:13] pins. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed number of
internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not
to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.
C6
TCK
Input
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
B7
TDI
Input
Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
A8
TDO
Output
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
C7
TMS
Input
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
D6
TRST
Input
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it
is not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module
on the device.
Note: For normal operation, connect TRST directly to VSS. If the design is
to be used in a debugging environment, TRST may be tied to VSS through a 1K
resistor.
B8
DE
Input/Output Debug Even (DE)— is an open-drain, bidirectional, active low signal.
As an input, it is a means of entering Debug mode of operation from an
external command controller. As an output, it is a means of
acknowledging that the chip has entered Debug mode.
56852 Technical Data, Rev. 8
14
Freescale Semiconductor
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