DSP56852VF120 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56852VF120

16-bit Digital Signal Controllers

Freescale Semiconductor 

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD

supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from

rising faster than VDDIO.

VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).

Typically this situation is avoided by using external discrete diodes in series between supplies, as shown

in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches

approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper

operation, the difference between supplies will typically be 0.8V and conduction through the diode chain

reduces to essentially leakage current. During supply sequencing, the following general relationship

should be adhered to:

VDDIO > VDD > (VDDIO - 2.1V)

In practice, VDDA is typically connected directly to VDDIO with some filtering.

3.3V

Supply Regulator

VDDIO, VDDA

VDD

1.8V

Regulator

Figure 4-3 Example Circuit to Control Supply Sequencing

4.4 AC Electrical Characteristics

Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for

all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of

VIH and VIL for an input signal are shown.

VIH

Low

Input Signal

Midpoint1

Fall Time

VIL

High

Rise Time

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 4-4 Input Signal Measurement References

90%

50%

10%

56852 Technical Data, Rev. 8

20

Freescale Semiconductor

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