DSP56852VF120 View Datasheet(PDF) - Freescale Semiconductor
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DSP56852VF120 Datasheet PDF : 48 Pages
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Table 4-1 Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Supply voltage, core
Supply voltage, IO
Supply voltage, analog
Digital input voltages
Analog input voltages (XTAL, EXTAL)
Current drain per pin excluding VDD, VSS, VDDA,
VSSA,VDDIO, VSSIO
Junction temperature
Storage temperature range
VDD1
VDDIO2
VDDIO2
VIN
VINA
I
VSS – 0.3
VSS + 2.0
VSSIO – 0.3
VSSA – 0.3
VSSIO + 4.0
VDDA + 4.0
VSSIO – 0.3
VSSA – 0.3
—
VSSIO + 5.5
VDDA + 0.3
10
TJ
-40
120
TSTG
-55
150
1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5V
Unit
V
V
V
mA
°C
°C
Table 4-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
Supply voltage for Logic Power
Supply voltage for I/O Power
Supply voltage for Analog Power
Ambient operating temperature
PLL clock frequency1
Operating Frequency2
Frequency of peripheral bus
Frequency of external clock
Frequency of oscillator
Frequency of clock via XTAL
Frequency of clock via EXTAL
VDD
VDDIO
VDDA
TA
fpll
fop
fipb
fclk
fosc
fxtal
fextal
1.62
1.98
V
3.0
3.6
V
3.0
3.6
V
-40
85
°C
—
240
MHz
—
120
MHz
—
60
MHz
—
240
MHz
2
4
MHz
—
240
MHz
2
4
MHz
1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
2. Master clock is derived from one of the following four sources:
fclk = fxtal when the source clock is the direct clock to EXAL
fclk = fpll when PLL is selected
fclk = fosc when the source clock is the crystal oscillator and PLL is not selected
fclk = fextal when the source clock is the direct clock to EXAL and PLL is not selected
56852 Technical Data, Rev. 8
16
Freescale Semiconductor
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