DSP56857 View Datasheet(PDF) - Freescale Semiconductor
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Description
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DSP56857 Datasheet PDF : 53 Pages
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Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No. Signal Name
Type
Description
77
TIO3
Input/Output Timer Input/Output (TIO3)—This pin can be independently configured to
be either a timer input source or an output flag.
GPIOG3
Input/Output
Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
15
IRQA
16
IRQB
Input
External Interrupt Request A and B—The IRQA and IRQB inputs are
asynchronous external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for Wired-OR operation.
10
MODE A
Input
Mode Select (MODE A)—During the bootstrap process MODE A selects
one of the eight bootstrap modes.
GPIOH0
Input/Output
Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
11
MODE B
Input
Mode Select (MODE B)—During the bootstrap process MODE B selects
one of the eight bootstrap modes.
GPIOH1
Input/Output
Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
12
MODE C
Input
Mode Select (MODE C)—During the bootstrap process MODE C selects
one of the eight bootstrap modes.
GPIOH2
Input/Output
Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
28
RESET
Input
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is latched
from the MODE A, MODE B, and MODE C pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not to
reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but
do not assert TRST.
27
RSTO
Output
Reset Output (RSTO)—This output is asserted on any reset condition
(external reset, low voltage, software or COP).
51
RXD0
Input
Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial
data and transfers it to the SCI 0 receive shift register.
GPIOE0
Input/Output
Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
56857 Technical Data, Rev. 6
Freescale Semiconductor
15
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