DSP56857 View Datasheet(PDF) - Freescale Semiconductor
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DSP56857 Datasheet PDF : 53 Pages
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No. Signal Name
Type
Description
40
TRST
Input
Test Reset (TRST)—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it is
not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module
on the device.
Note: For normal operation, connect TRST directly to VSS. If the design is to
be used in a debugging environment, TRST may be tied to VSS through a 1K
resistor.
39
DE
Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of operation
from an external command controller. As an output, it is a means of
acknowledging that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
56857 Technical Data, Rev. 6
20
Freescale Semiconductor
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