DSP56857 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56857 Datasheet PDF : 53 Pages
| |||
Introduction
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No. Signal Name
Type
Description
3
SCK
Input/Output SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate
clock for the SPI. This gated clock signal is an input to a slave device and
is generated as an output by a master device. Slave devices ignore the
SCK signal unless the SS pin is active low. In both master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled on
the opposite edge where data is stable. The driver on this pin can be
configured as an open-drain driver by the SPI’s WOM bit when this pin is
configured for SPI operation. When using Wired-OR mode, the user must
provide an external pull-up device.
GPIOF2
Input/Output
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
4
SS
Input
SPI Slave Select (SS)—This input pin selects a slave device before a
master device can exchange data with the slave device. SS must be low
before data transactions and must stay low for the duration of the
transaction. The SS line of the master must be held high.
GPIOF3
Input/Output
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
20
XTAL
Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.
21
EXTAL
Input
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2
26
CLKO
Output
Clock Output (CLKO)—This pin outputs a buffered clock signal. When
enabled, this signal is the system clock divided by four.
44
TCK
Input
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
42
TDI
Input
Test Data Input (TDI)—This input pin provides a serial input data stream
to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
41
TDO
Output(Z)
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
43
TMS
Input
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
56857 Technical Data, Rev. 6
Freescale Semiconductor
19
Share Link: 