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88E1116R-NNC1 View Datasheet(PDF) - Marvell Semiconductor

Part Name
Description
Manufacturer
88E1116R-NNC1
Marvell
Marvell Semiconductor Marvell
88E1116R-NNC1 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Alaska® 88E1116R Technical Product Brief
Gigabit Ethernet Transceiver
Table 6: Clock/Configuration/Reset/I/O
64-QFN
Pin #
64
1
2
3
38
Pin Name
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
XTAL_IN
Pin
Ty p e
I
I
I
I
I
39
XTAL_OUT 0
10
RESETn
I
57
VREF
I
Description
Hardware Configuration
Hardware Configuration
Hardware Configuration
Hardware Configuration
Reference Clock. 25 MHz ± 50 ppm tolerance crystal reference or oscillator
input.
NOTE: If AVDDC is tied to 1.8V, then the XTAL_IN pin is not 2.5V/3.3V tolerant.
If AVDDC is tied to 2.5V, then the XTAL_IN pin is not 3.3V tolerant.
Reference Clock. 25 MHz ± 50 ppm tolerance crystal reference. When the
XTAL_OUT pin is not connected, it should be left floating.
Hardware reset. Active low.
0 = Reset
1 = Normal
RGMII input voltage reference.
Must be set to VDDOR/2 when used as 1.8V HSTL, 2.5V SSTL_2, and 3.3V.
Set to VDDOR when used as 2.5V LV CMOS.
Doc. No. MV-S105539-00, Rev. --
Page 10
Document Classification: Proprietary Information
Copyright © 2011 Marvell
May 9, 2011, Advance

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