A8351601 View Datasheet(PDF) - AMIC Technology
Part Name
Description
Manufacturer
A8351601 Datasheet PDF : 44 Pages
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A8351601 Series
Note 1:
M1
0
0
1
1
1
M0
Operating mode
0
Mode 0. (13-bit Timer)
1
Mode 1. (16-bit Timer/Counter)
0
Mode 2. (8-bit auto-load Timer/Counter)
1
Mode 3. (Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit Timer/
Counter controller by the standard Timer 0 control bits. TH0 is an
8-bit Timer and is controlled by Timer 1 control bits.)
1
Mode 3. (Timer/Counter 1 stopped).
SCON:
Serial Port Control Register. Bit Addressable.
7
6
SM0
SM1
Register Description:
SM0
SCON.7
SM1
SCON.6
SM2
SCON.5
REN
TB8
RB8
TI
RI
SCON.4
SCON.3
SCON.2
SCON.1
SCON.0
5
4
3
2
1
0
SM2
REN
TB8
RB8
TI
RI
Serial port mode specifically. (1)
Serial port mode specifically. (1)
Enable the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2
is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if
SM2=1 then RI will not be activated if valid stop bit was not received. In mode 0, SM2
should be 0.
Set/Cleared by software to Enable/Disable reception.
The 9th bit that will be transmitted in mode 2 and 3. Set/Cleared by software.
In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is
the stop bit that was received. In mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by
software.
Note:
SM0
0
0
1
1
SM1
0
1
0
1
MODE
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Baud rate
Fosc/12
Variable
Fosc/64 or Fosc/32
Variable
T2CON:
Timer/Counter 2 Control Register. Bit Addressable.
7
6
TF2
EXF2
Register Description:
TF2
T2CON.7
EXF2
T2CON.6
RCLK
T2CON.5
TCLK
T2CON.4
5
4
3
2
RCLK
TCLK
EXEN2
TR2
1
C/ T2
0
CP/ RL2
Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition
on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the
transmit clock.
(July, 2002, Version 1.0)
10
AMIC Technology, Inc.
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