AD9845AJST View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9845AJST

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

VD

012012012...

LINE n

...01201

012012012...

LINE n+1

HD

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2

Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence

AD9845A

5 PIXEL MIN

VD

OBSOLETE HD

SHP

5 PIXEL MIN

3ns MIN

PxGA GAIN

GAINX GAIN0

GAIN1 GAIN2 GAIN0

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.

Figure 13. PxGA Mode 3 (3-Color) Detailed Timing

GAINX

GAIN0

GAIN1

VD

LINE n

LINE n+1

01230123012...

...01230

012301230123...

HD

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence

VD

HD

SHP

5 PIXEL MIN

5 PIXEL MIN

3ns MIN

PxGA GAIN

GAINX GAIN0

GAIN1 GAIN2

GAIN0

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.

Figure 15. PxGA Mode 4 (4-Color) Detailed Timing

GAINX

GAIN0

GAIN1

REV. 0

–11–

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