AD9923A View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

THEORY OF OPERATION

Figure 14 shows the typical system block diagram for the

AD9923A in master mode. The CCD output is processed by

the AD9923A AFE circuitry, which consists of a CDS, VGA,

black level clamp, and ADC. The digitized pixel information is

sent to the digital image processor chip that performs the post-

processing and compression. To operate the CCD, CCD timing

parameters are programmed into the AD9923A from the system

microprocessor through the 3-wire serial interface. The AD9923A

generates the CCD horizontal, vertical, and the internal AFE

clocks from the system master clock CLI. The CLI is provided

by the image processor or external crystal. External synchroniza-

tion is provided by a sync pulse from the microprocessor, which

resets internal counters and resyncs the VD and HD outputs.

Alternatively, the AD9923A can be operated in slave mode, in

which the VD and HD are provided externally from the image

processor. In this mode, the AD9923A timing is synchronized

with VD and HD.

The H-drivers for HL, H1 to H4, and RG are included in the

AD9923A, allowing these clocks to be directly connected to the

CCD. An H-driver voltage, HVDD, of up to 3.3 V is supported.

An external V-driver is required for the vertical transfer clocks,

the sensor gate pulses, and the substrate clock.

The AD9923A also includes programmable MSHUT and

STROBE outputs that can be used to trigger mechanical shutter

and strobe (flash) circuitry.

Figure 15 and Figure 16 show the maximum horizontal and

vertical counter dimensions for the AD9923A. Internal hori-

zontal and vertical clocking is controlled by these counters to

specify line and pixel locations. The maximum HD length is

8192 pixels per line, and the maximum VD length is 4096 lines

per field.

V1 TO V13, SUBCK

HL, H1 TO H4, RG, VSUB

CCD

CCDIN

MSHUT

STROBE

AD9923A

AFETG +

V-DRIVER

D[0:11]

DCLK

HD, VD

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

SYNC

SERIAL

INTERFACE

MICRO-

PROCESSOR

Figure 14. Typical System Block Diagram, Master Mode

MAXIMUM

COUNTER

DIMENSIONS

13-BIT HORIZONTAL = 8192 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 15. Vertical and Horizontal Counters

MAX VD LENGTH IS 4096 LINES

VD

MAX HD LENGTH IS 8192 PIXELS

HD

CLI

Figure 16. Maximum VD/HD Dimensions

Rev. A | Page 14 of 84

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