AD9923A View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9923A Datasheet PDF : 84 Pages
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AD9923A
Table 12. CLPOB and PBLK Pattern Registers
Register
Length (Bits) Range
CLPOBPOL
1
High/low
PBLKPOL
1
High/low
CLPOBTOG1
13
0 to 8191 pixel location
CLPOBTOG2
13
0 to 8191 pixel location
PBLKTOG1
13
0 to 8191 pixel location
PBLKBTOG2
13
0 to 8191 pixel location
CLPMASKSTART 12
0 to 4095 line location
CLPMASKEND 12
0 to 4095 line location
PBLKMASKSTART 12
0 to 4095 line location
PBLKMASKEND 12
0 to 4095 line location
Description
Starting polarity of CLPOB for each V-sequence
Starting polarity of PBLK for each V-sequence
First CLPOB toggle position within the line for each V-sequence
Second CLPOB toggle position within the line for each V-sequence
First PBLK toggle position within the line for each V-sequence
Second PBLK toggle position within the line for each V-sequence
CLPOB masking area—starting line within the field (maximum of three areas)
CLPOB masking area—ending line within the field (maximum of three areas)
PBLK masking area—starting line within the field (maximum of three areas)
PBLK masking area—ending line within the field (maximum of three areas)
HD
CLPOB 1
PBLK
2
3
ACTIVE
PROGRAMMABLE SETTINGS:
1START POLARITY (CLAMP AND BLANK REGIONS ARE ACTIVE LOW).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
Figure 23. Clamp and Preblank Pulse Placement
ACTIVE
VD
0 12
HD
CLPOB
NO CLPOB SIGNAL
FOR LINES 6 TO 8
NO CLPOB SIGNAL
FOR LINE 600
597 598
CLPMASKSTART1 = 6
CLPMASKEND1 = 8
CLPMASKSTART2 = CLPMASKEND2 = 600
Figure 24. CLPOB Masking Example
VD
0 12
HD
PBLK
NO PBLK SIGNAL
FOR LINES 6 TO 8
NO PBLK SIGNAL
FOR LINE 703
700 701
PBLKMASKSTART1 = 6 PBLKMASKEND1 = 8 PBLKMASKSTART2 = PBLKMASKEND2 = 703
Figure 25. PBLK Masking Example
Rev. A | Page 19 of 84
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