AHA4013B View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

AHA4013B

12.5 MBytes/sec Reed-Solomon Error Correction Device

Unspecified 

Advanced Hardware Architectures, Inc.

Data of one block must be fully emptied L × Co clocks after the start of empty process.

All of the conditions on the maximum delay given in Equation 4 must be satisfied. If any are not, the

output data stream will begin to inhibit ECC processing. Eventually this will cause the input buffer to over

fill and RDYIN to become inactive.

Figure 4: Burst and Continuous Operations

(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order.

Block i is the first input block, block i + 1 is second input block. XK − 1 is the first input message byte of a block. Yo

is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst

Operation - Caveats.)

Input Data:

Output Data:

Burst Operation

Block i+1

Y0 . . . . . . . . . . X K-1

Block i+1

Y0 . . . . . . . . . . X K-1

1

2

Block i

Y0 . . . . . . . . . . . . . . . . . . X K-1

Block i

Y0 . . . . . . . . . . X K-1

Input Data:

Output Data:

Processing Latency

Continuous Operation

Block i+3

Block i+2

Block i+1

Block i

Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1

Block i+3

Block i+2

Block i+1

Block i

Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1

For a 50 MHz system using the required clocks per byte, maximum latencies and data rates for forward

order output are shown in the table for continuous operation. Input and Output rates are assumed the same

in this table. Note: Other frequency operations are also possible.

Table 3: Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward

Output Order

CHECK BYTES ‘R’ = 20

BLOCK

LENGTHS ‘N’

MINIMUM

REQUIRED

(clocks/byte)

MAXIMUM

DATA RATE

(MBytes/sec)

MAXIMUM

LATENCY

(µsecs)

25

6

8.34

5.08

50

5

10.00

7.75

100

4

12.50

12.18

150

4

12.50

17.52

200

4

12.50

22.86

225

4

12.50

25.52

255

4

12.50

28.72

CHECK BYTES ‘R’ = 2

MINIMUM MAXIMUM MAXIMUM

REQUIRED DATA RATE LATENCY

(clocks/byte) (MBytes/sec) (µsecs)

5

10.0

4.26

5

10.0

7.39

4

12.5

11.82

4

12.5

17.16

4

12.5

22.50

4

12.5

25.16

4

12.5

28.36

For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 50 MHz clock.

Note: Other frequency operations are also possible.

Page 10 of 24

PS4013B-0600

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