AHA4013B View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
AHA4013B Datasheet PDF : 28 Pages
| |||
Advanced Hardware Architectures, Inc.
Figure 10: Data Output
CLK
DO, ERR
DSON
RDYON
3
3
valid
12
12
valid
12
12
3
3
valid
valid
12
12
12
4
4
valid
12
4
NUMBER
1
2
3
4
DESCRIPTION
DSON setup time
DSON hold time
DO output delay
RDYON output delay
MINIMUM
8
2
3
3
MAXIMUM
13
13
UNITS
nsec
nsec
nsec
nsec
CRTN is valid for an RS block when the first message byte, XK−1, is strobed out of the chip. Figure 11
shows Reverse Order output. In this operation, CRTN is valid on the last byte of the block from the Output
Buffer. In this example only message bytes are output, no check bytes.
Figure 11: CRTN Timing - Reverse Order Output
CLK
DO
DSON
CRTN
RDYON
3
3
Block m
Byte XK-3
12
12
Block m
Byte XK-2
12
12
3
3
Block m
Byte XK-1
Block m+1
Byte X0
12
12
12
4 error
VALID
See Note
correctable
4
4
Block m+1
Byte X1
12
4
Note: CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the
error threshold, P, CRTN is inactive (high).
NUMBER
1
2
3
4
DESCRIPTION
DSON setup time
DSON hold time
DO output delay
RDYON, CRTN output delay
MINIMUM
7
2
3
3
MAXIMUM
13
13
UNITS
nsec
nsec
nsec
nsec
PS4013B-0600
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