AHA4013B View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
AHA4013B Datasheet PDF : 28 Pages
| |||
Advanced Hardware Architectures, Inc.
Figure 8: Data Input - Buffer Always Ready
CLK
RSTN
DI
DSIN
ERASE
RDYIN
12
12
12
12
12
12
12
12
valid
valid
valid
valid
valid
12 12
valid
high = erase
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If
RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high
in four sample clocks.
NUMBER
1
2
DESCRIPTION
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
MINIMUM
7
0
MAXIMUM
UNITS
nsec
nsec
Figure 9: Data Input - Buffer Not Ready
CLK
RSTN
DI
DSIN
RDYIN
12
12
12
valid
3
12
12
12
12
valid
valid
valid
valid
3
3
3
NUMBER
1
2
3
DESCRIPTION
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
RDYIN output delay
MINIMUM
7
0
MAXIMUM
13
UNITS
nsec
nsec
nsec
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 9.
3.4 DATA OUTPUT
The DO pins are driven from a register clocked
on the rising edge of CLK.
Valid data on the DO pins is indicated by
RDYON being active. When RDYON is inactive,
data on the DO pins is undefined, and DSON is
ignored. The DSON signal acknowledges receiving
the data and is used by the device to internally
increment the address counter and output the next
location in the buffer. This data output timing is
shown in Figure 10.
Page 14 of 24
PS4013B-0600
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