CY8C20160-LDX1I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C20160-LDX1I Datasheet PDF : 46 Pages
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CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts - 16-Pin SOIC
Figure 2. 16-pin SOIC (150 Mils) pinout [4]
Pin Definitions
16-pin SOIC [4, 5]
Pin No.
1
2
Name
GP0[3]
CSint
3
GP0[4]
4
GP0[0]
5
GP0[1]
6
I2C SCL
7
I2C SDA
8
GP1[0]
9
GP1[1] [6]
10
VSS
11
GP1[2] [6]
12
GP1[3]
13
GP1[4]
14
XRES
15
GP0[2]
16
VDD
Description
Configurable as CapSense or GPIO
Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF.
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I2C clock
I2C data
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground connection
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Active high external reset with internal pull-down
Configurable as CapSense or GPIO
Supply voltage
Notes
4. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
5. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
6. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *J
Page 4 of 46
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