Specifications
External Clock Operation
EXTERNAL CLOCK OPERATION
The DSP56011 system clock is externally supplied via the EXTAL pin. Timings shown
in this document are valid for clock rise and fall times of 3 ns maximum. The 81 MHz
P R E L I M I N A R Y speed allows the DSP56011 to take advantage of the 27 MHz system clock in DVD
applications.
Table 2-5 External Clock (EXTAL)
81 MHz
95 MHz
No.
Characteristics
Sym.
Unit
Min Max Min Max
Frequency of external clock EXTAL
1 External clock input high—EXTAL
• With PLL disabled
(46.7%–53.3% duty cycle)
• With PLL enabled
(42.5%–57.5% duty cycle)
EF
0
81
0
ETH
5.8
∞
4.9
5.2 235500 4.5
2 External clock input low—EXTAL
• With PLL disabled
(46.7%–53.3% duty cycle)
• With PLL enabled
(42.5%–57.5% duty cycle)
ETL
5.8
∞
4.9
5.2 235500 4.5
3 External clock cycle time
• With PLL disabled
• With PLL enabled
ETC
12.3
∞
10.5
12.3 409600 10.5
4 Instruction cycle time = ICYC = 2 × TC
• With PLL disabled
• With PLL enabled
ICYC
24.7
∞
21.0
24.7 819200 21.0
Note: EXTAL input high and input low are measured at 50% of the input transition.
95 MHz
∞
ns
235500 ns
∞
ns
235500 ns
∞
ns
409600 ns
∞
ns
819200 ns
EXTAL
1
2
ETH
ETL
3
ETC
4
AA0250
Figure 2-1 External Clock Timing
Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-5