Freescale Semiconductor, Inc.
Specifications
Internal Clocks
2.6 INTERNAL CLOCKS
Table 2-4 Internal Clocks
Characteristics
Symbo
l
Expression1, 2
Min
Typ
Max
Internal operation frequency
f
—
(Ef × MF)/
—
with PLL enabled
(PDF × DF)
Internal operation frequency
f
—
Ef/2
—
with PLL disabled
Internal clock high period
TH
• With PLL disabled
—
ETC
—
• With PLL enabled and
MF ≤ 4
0.49 × ETC ×
—
0.51 × ETC ×
PDF × DF/MF
PDF × DF/MF
• With PLL enabled and
MF > 4
0.47 × ETC ×
—
0.53 × ETC ×
PDF × DF/MF
PDF × DF/MF
Internal clock low period
• With PLL disabled
TL
—
ETC
—
• With PLL enabled and
MF ≤ 4
0.49 × ETC ×
—
0.51 × ETC ×
PDF × DF/MF
PDF × DF/MF
• With PLL enabled and
MF > 4
0.47 × ETC ×
—
0.53 × ETC ×
PDF × DF/MF
PDF × DF/MF
Internal clock cycle time with
TC
—
ETC × PDF ×
—
PLL enabled
DF/MF
Internal clock cycle time with
TC
—
2 × ETC
—
PLL disabled
Instruction cycle time
ICYC
—
TC
—
Notes: 1. DF = Division Factor
Ef = External frequency
ETC = External clock cycle
MF = Multiplication Factor
PDF = Predivision Factor
TC = internal clock cycle
2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion
of the PLL.
MOTOROLA
DSP56364 Advance Information
2-5
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