Specifications
Freescale Semiconductor, Inc.
EXTERNAL CLOCK OPERATION
2.7 EXTERNAL CLOCK OPERATION
The DSP56364 system clock is an externally supplied square wave voltage source connected to
EXTAL(See Figure 2-1).
EXTAL
VILC
ETH
2
ETL
3
4
ETC
Midpoint
VIHC
Note: The midpoint is 0.5 (VIHC + VILC).
Figure 2-1 External Clock Timing
Table 2-5 Clock Operation
No.
Characteristics
Symbol
Min
Max
Frequency of EXTAL (EXTAL Pin Frequency)
1 The rise and fall time of this external clock should be
3 ns maximum.
EXTAL input high1, 2
2
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle6)
EXTAL input low1, 2
3
• With PLL disabled (46.7%–53.3% duty cycle6)
• With PLL enabled (42.5%–57.5% duty cycle6)
EXTAL cycle time2
4
• With PLL disabled
• With PLL enabled
Ef
0
100.0
ETH
4.67 ns
∞
4.25 ns 157.0 µs
ETL
4.67 ns
∞
4.25 ns 157.0 µs
ETC
10.00 ns
∞
10.00 ns 273.1 µs
Notes: 1. Measured at 50% of the input transition
2. The maximum value for PLL enabled is given for minimum VCO and maximum MF.
2-6
DSP56364 Advance Information
MOTOROLA
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