Reset, Stop, Mode Select, and Interrupt Timing
3.9 Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1
No
Characteristics
Expression2
8 Delay from RESET assertion to all pins at reset value3
9 Required RESET duration4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
• During normal operation
10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)5
• Minimum
• Maximum
11 Synchronous reset setup time from RESET
deassertion to CLKOUT Transition 1
• Minimum
• Maximum
12 Synchronous reset deasserted, delay time from the
CLKOUT Transition 1 to the first external address
output
• Minimum
• Maximum
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt request assertion
width
16 Minimum edge-triggered interrupt request deassertion
width
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first
interrupt instruction execution
—
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
20.25 TC + 7.50
TC
3.25 × TC + 2.0
20.25 TC + 7.5
4.25 × TC + 2.0
7.25 × TC + 2.0
10 × TC + 5.0
100 MHz
Min
Max
—
26.0
120 MHz
Unit
Min Max
26.0 ns
500.0
10.0
750
750
25.0
25.0
— 416.7 — ns
—
8.3 — µs
—
625 — µs
—
625 — µs
—
20.8 — ns
—
20.8 — ns
34.5
—
29.1
ns
—
211.5
176.2 ns
5.9
—
ns
—
10.0
ns
33.5
—
ns
—
207.5
ns
30.0
—
30.0
ns
0.0
—
0.0
ns
6.6
—
5.5
ns
6.6
—
5.5
ns
44.5
—
37.4
ns
74.5
—
62.4
ns
105.0
—
88.3
ns
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-7