DSP56362 View Datasheet(PDF) - Freescale Semiconductor
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DSP56362 Datasheet PDF : 152 Pages
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Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)
No
Characteristics
Expression2
100 MHz
Min
Max
120 MHz
Unit
Min Max
27 Interrupt Requests Rate
• HI08, ESAI, SHI, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ, NMI (level trigger)
12TC
8TC
8TC
12TC
—
120.0 — 100.0 ns
—
80.0
— 66.7 ns
—
80.0
— 66.7 ns
—
120.0 — 100.0 ns
28 DMA Requests Rate
• Data read from HI08, ESAI, SHI
• Data write to HI08, ESAI, SHI
• Timer
• IRQ, NMI (edge trigger)
6TC
—
60.0
— 50.0 ns
7TC
—
70.0
— 58.0 ns
2TC
—
20.0
— 16.7 ns
3TC
—
30.0
— 25.0 ns
29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory (DMA source) access address out
valid
4.25 × TC + 2.0
44.0
—
37.4 — ns
1 VCC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF
2 Use expression to compute maximum value.
3 Periodically sampled and not 100% tested.
4 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the
EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted
and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both
by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When
the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device
circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize
this state to the shortest possible duration.
5 If PLL does not lose lock.
6 When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when
using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
7 These values depend on the number of wait states (WS) selected.
8 WS = number of wait states (measured in clock cycles, number of TC.
9 This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and
oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before
executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to
set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The
PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel
with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion. PLC value for PLL disable is 0.
The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency
(i.e., for 100 MHz it is 4096/100 MHz = 40.96µs). During the stabilization period, TC, TH, and TL will not be constant, and their
width may vary, so timing may vary as well.
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-9
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