DSP56362 View Datasheet(PDF) - Freescale Semiconductor
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DSP56362 Datasheet PDF : 152 Pages
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Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)
No
Characteristics
Expression2
19 Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for
level sensitive fast interrupts6
(3.75 + WS) × TC –
10.94
100 MHz
Min
Max
—
Note7
120 MHz
Unit
Min Max
— Note 7 ns
20 Delay from RD assertion to interrupt request
deassertion for level sensitive fast interrupts6
(3.25 + WS) × TC –
—
Note 7 — Note 7
10.94
21 Delay from WR assertion to interrupt request
deassertion for level sensitive fast interrupts6 8
• DRAM for all WS
• SRAM WS =1
• SRAM WS=2, 3
• SRAM WS ≥ 4
22 Synchronous interrupt setup time from IRQA, IRQB,
IRQC, IRQD, NMI assertion to the CLKOUT Transition 2
(WS + 3.5) × TC –
10.94
(WS + 3.5) × TC –
10.94
1.75 × TC – 4.0
2.75 × TC – 4.0
0.6 × TC – 0.1
—
Note 7 — Note 7 ns
—
Note 7 — Note 7 ns
—
Note 7 — Note 7 ns
—
Note 7 — Note 7 ns
5.9
4.9 — ns
23 Synchronous interrupt delay time from the CLKOUT
Transition 2 to the first external address output valid
caused by the first instruction fetch after coming out of
Wait Processing state
• Minimum
• Maximum
9.25 × TC + 1.0
24.75 × TC + 5.0
93.5
—
78.1 — ns
—
252.5 — 211.2 ns
24 Duration for IRQA assertion to recover from Stop state
0.6 × TC − 0.1
5.9
—
4.9 — ns
25 Delay from IRQA assertion to fetch of first instruction
(when exiting Stop)9, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and PLC × ETC × PDF +
1.3
Stop delay is enabled (OMR Bit 6 = 0)
(128 K − PLC/2) × TC
13.6
—
— ms
• PLL is not active during Stop (PCTL Bit 17 = 0) and PLC × ETC × PDF + 232.5 ns 12.3 ms —
—
Stop delay is not enabled (OMR Bit 6 = 1)
(23.75 ± 0.5) × TC
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies
No Stop Delay)
(8.25 ± 0.5) × TC
77.5
87.5 64.6 72.9 ns
26 Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)9, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and PLC × ETC × PDF + 13.6
Stop delay is enabled (OMR Bit 6 = 0)
(128K − PLC/2) × TC
• PLL is not active during Stop (PCTL Bit 17 = 0) and PLC × ETC × PDF + 12.3
Stop delay is not enabled (OMR Bit 6 = 1)
(20.5 ± 0.5) × TC
• PLL is active during Stop (PCTL Bit 17 = 1) (implies
5.5 × TC
55.0
no Stop delay)
—
ms
—
ms
—
45.8 — ns
DSP56362 Technical Data, Rev. 4
3-8
Freescale Semiconductor
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