DSP56300FM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56300FM

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

AC Electrical Characteristics

5 This characteristic does not apply to PCAP.

6 Section 5, "Design Considerations" provides a formula to compute the estimated current requirements in Normal

mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on

synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results

of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ

= 105°C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 105°C.

7 In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop

state.

8 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to

float).

3.5 AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum

of 0.3 V and a

shown in Note

V8 IoHf

minimum of

the previous

2.4 V

table.

for all pins

AC timing

except EXTAL, which is

specifications, which are

tested using the input

referenced to a device

levels

input

signal, are measured in production with respect to the 50% point of the respective input signal’s transition.

DSP56364 output levels are measured with the production test machine VOL and VOH reference levels set

at 0.4 V and 2.4 V, respectively.

NOTE

Although the minimum value for the frequency of EXTAL is 0 MHz, the

device AC test conditions are 15 MHz and rated speed.

3.6 Internal Clocks

Table 3-4 Internal Clocks

Characteristics

Symbol

Min

Internal operation frequency with PLL enabled

f

—

Internal operation frequency with PLL disabled

f

Internal clock high period

TH

• With PLL disabled

• With PLL enabled and MF ≤ 4

• With PLL enabled and MF > 4

—

—

0.49 × ETC ×

PDF × DF/MF

0.47 × ETC ×

PDF × DF/MF

Expression1, 2

Typ

(Ef × MF)/

(PDF × DF)

Ef/2

ETC

—

—

Max

—

—

—

0.51 × ETC ×

PDF × DF/MF

0.53 × ETC ×

PDF × DF/MF

DSP56364 Technical Data, Rev. 4.1

3-4

Freescale Semiconductor

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