EBE10RD4AGFA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBE10RD4AGFA Datasheet PDF : 23 Pages
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EBE10RD4AGFA
-6E
-5C
-4A
Frequency (Mbps)
667
533
400
Parameter
Symbol min.
max.
min.
max.
min.
max.
Unit Notes
Active to precharge command tRAS 45
70000
45
70000
40
70000
ns
Active to auto-precharge delay tRAP tRCD min.
tRCD min.
tRCD min.
ns
Active bank A to active bank B
command period
tRRD
7.5
7.5
7.5
ns
Write recovery time
tWR 15
15
15
ns
Auto precharge
precharge time
write
recovery
+
tDAL
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tCK 1
Internal write to read command
delay
tWTR
7.5
7.5
10
ns
Internal read to precharge
command delay
tRTP 7.5
7.5
7.5
ns
Exit self refresh to a non-read
command
tXSNR
tRFC + 10
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read
command
tXSRD 200
200
200
tCK
Exit precharge power down to
any non-read command
tXP
2
2
2
tCK
Exit active power down to read
command
tXARD
2
2
2
tCK 3
Exit active power down to read
command
tXARDS 7− AL
(slow exit/low power mode)
6 − AL
6 − AL
tCK 2, 3
CKE minimum pulse
and low pulse width)
width
(high
tCKE
3
3
3
tCK
Output impedance test driver
delay
tOIT
0
12
0
12
0
12
ns
Auto refresh to active/auto
refresh command time
tRFC 105
105
105
ns
Average
(0°C ≤
periodic refresh
TC ≤ +85°C)
interval
tREFI
7.8
7.8
7.8
µs
(+85°C < TC ≤ +95°C)
tREFI
3.9
3.9
3.9
µs
Minimum time clocks remains
ON after CKE asynchronously
drops low
tDELAY
tIS + tCK +
tIH
tIS + tCK +
tIH
tIS + tCK +
tIH
ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS
CK
/DQS
/CK
tDS tDH
tDS tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0795E20 (Ver. 2.0)
17
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