EBE10RD4AGFA View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EBE10RD4AGFA

1GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE10RD4AGFA

ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)

Parameter

Symbol

min.

max.

Unit Notes

ODT turn-on delay

tAOND

2

2

tCK

ODT turn-on

-6E

tAON

tAC(min)

tAC(max) + 700

ps 1

-5C, -4A

tAON

tAC(min)

tAC(max) + 1000

ps 1

ODT turn-on (power down mode)

tAONPD

tAC(min) + 2000 2tCK + tAC(max) + 1000

ps

ODT turn-off delay

tAOFD

2.5

2.5

tCK

ODT turn-off

tAOF

tAC(min)

tAC(max) + 600

ps 2

ODT turn-off (power down mode)

tAOFPD

tAC(min) + 2000 2.5tCK + tAC(max) + 1000

ps

ODT to power down entry latency

tANPD

3

3

tCK

ODT power down exit latency

tAXPD

8

8

tCK

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

AC Input Test Conditions

Parameter

Symbol

Value

Unit

Notes

Input reference voltage

VREF

0.5 × VDDQ

V

1

Input signal maximum peak to peak swing VSWING(max.)

1.0

V

1

Input signal maximum slew rate

SLEW

1.0

V/ns

2, 3

Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the

device under test.

2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)

(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in

the below figure.

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive

transitions and VIH(AC) to VIL(AC) on the negative transitions.

Start of falling edge input timing

Start of rising edge input timing

VDDQ

VIH (AC)(min.)

VSWING(max.)

VIH (DC)(min.)

VREF

VIL (DC)(max.)

VIL (AC)(max.)

VSS

∆TF

∆TR

VIH (DC)(min.) − VIL (AC)(max.)

Falling slew =

∆TF

VIH (AC) min. − VIL (DC)(max.)

Rising slew =

∆TR

AC Input Test Signal Wave forms

Measurement point

DQ

VTT

RT =25 Ω

Output Load

Data Sheet E0795E20 (Ver. 2.0)

18

Share Link: