HT45F4M
Lithium Battery Backup Power ASSP MCU
Symbol
Parameter
IOH2
I/O Port Source Current
(PB4, PB5)
Test Conditions
VDD
Conditions
3V VOH= 0.9VDD
5V VOH= 0.9VDD
VLVR
Low Voltage Reset Voltage —
—
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
ILVR
ILVD
RPH
LVDEN= 1, VLVD = 2.7V
Low Voltage Detector
Voltage
LVDEN= 1, VLVD = 3.0V
— LVDEN= 1, VLVD = 3.3V
LVDEN= 1, VLVD = 3.6V
LVDEN= 1, VLVD = 4.0V
Additional Power
Consumption if LVR is
used
3V
LVR enable
5V
Additional Power
3V LVD disable → LVD enable
Consumption if LVD is used 5V (LVR enable)
Pull-high Resistance for
3V
—
I/O Ports
5V
—
Note: LVR is aways enabled (HALT mode disabled) fixed @ 2.55V.
A.C. Characteristics
Symbol
fCPU
fSYS
fHIRC
fSUB
tTIMER
tINT
tLVR
tLVD
tLVDS
tSRESET
tEERD
tEEWR
tSST
Parameter
Test Conditions
VDD
Conditions
Operating Clock
2.7V~5.5V
—
4.5V~5.5V
2.7V~5.5V
System Clock (HIRC)
—
4.5V~5.5V
5V Ta= 25°C
HIRC Frequency (note)
4.0V~5.5V Ta= -10°C~85°C
3.6V~5.5V Ta= -40°C~85°C
System Clock (LIRC)
5V Ta= 25°C
2.7V~5.5V Ta= -40°C~85°C
TCKn Input Pin Minimum
Pulse Width
—
—
Interrupt Minimum Pulse Width —
—
Low Voltage Width to Reset
—
—
Low Voltage Width to Interrupt
—
—
LVDO Stable Time
—
For LVR enable,
LVD off → on
Software Reset Width to Reset —
—
EEPROM Read Time
—
—
EEPROM Write Time
—
—
System Start-up Timer Period
(Wake-up from HALT, fSYS off
at HALT state)
—
fSYS= HIRC
—
fSYS= LIRC
System Start-up Timer Period
(Wake-up from HALT, fSYS on
—
—
at HALT state)
Min. Typ. Max. Unit
-8
-16
—
mA
-20 -40
—
mA
-5%×
Typ.
2.55
-5%×
Typ.
V
2.7
V
3.0
V
-5%×
Typ.
3.3
-5%×
Typ.
V
3.6
V
4.0
V
—
30
45
μA
—
60
90
μA
—
30
45
μA
—
60
90
μA
20
60 100 kΩ
10
30
50
kΩ
Min.
DC
DC
—
—
-2%
-5%
-10%
-10%
-30%
—
1
120
20
15
45
—
—
—
—
Typ.
—
—
—
—
30
30
30
32
32
30
3.3
240
45
—
90
2
2
16
2
Ta= 25°C
Max. Unit
7.5
15
7.5
15
+2%
+5%
+10%
+10%
+60%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
kHz
— ns
5
μs
480 μs
90 μs
— μs
120 μs
4
tSYS
4 ms
—
tSYS
—
tSYS
—
2
—
tSYS
Rev. 1.10
11
January 15, 2013