Electrical Characteristics
Table 13 shows the i.MX51 operating ranges.
Table 13. i.MX51 Operating Ranges
Symbol
Parameter
Minimum1 Nominal2 Maximum1 Unit
VDDGP
MCIMX51xD products
(Consumer)
ARM core supply voltage
0 ≤ fARM ≤ 167 MHz
ARM core supply voltage
167 < fARM ≤ 800 MHz
ARM core supply voltage
Stop mode
0.8
0.85
1.15
V
1.05
1.1
1.15
V
0.8
0.85
1.15
V
VDDGP
MCIMX51xC products
(Industrial)
ARM core supply voltage
0 < fARM ≤ 600 MHz
ARM core supply voltage
Stop mode
0.95
1.0
1.10
V
0.90
0.95
1.05
V
VCC
Peripheral supply voltage High Performance
1.175
1.225
1.275
V
MCIMX51xD products Mode (HPM) The clock frequencies are derived
(Consumer)
from AXI and AHB buses using 133 or 166 MHz
(as needed). The DDR clock rate is 200 MHz.
Note: For detailed information about the use of
133 or 166 MHz clocks, see i.MX51 Multimedia
Applications Processor Reference Manual
(MCIMX51RM).
Peripheral supply voltage Low Performance
1.00
1.05
1.275
V
Mode (LPM) The clock frequencies are derived
from AXI and AHB buses at 44 MHz and a DDR
clock rate of DDR Clock/3. DDR2 does not
support frequencies below 125 MHz per
JEDEC.
Peripheral supply voltage—Stop mode
0.9
0.95
1.275
V
VCC
Peripheral supply voltage High Performance
1.175
1.225
1.275
V
MCIMX51xC products Mode (HPM) The clock frequencies are derived
(Industrial)
from AXI and AHB buses using 133 or 166 MHz
(as needed). The DDR clock rate is 200 MHz.
Note: For detailed information about the use of
133 or 166 MHz clocks, see i.MX51 Multimedia
Applications Processor Reference Manual
(MCIMX51RM).
Peripheral supply voltage—Stop mode
0.90
0.95
1.275
V
VDDA
Memory arrays voltage—Run Mode
1.15
1.20
1.275
V
Memory arrays voltage—Stop Mode
0.9
0.95
1.275
V
VDD_DIG_PLL_A
VDD_DIG_PLL_B
PLL Digital supplies
1.15
1.2
1.35
V
VDD_ANA_PLL_A
VDD_ANA_PLL_B
PLL Analog supplies
1.75
1.8
1.95
V
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
19