KS9287 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

KS9287

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

KS9287

FWSEL, WSEL

Frame Sync protection window size (Refer to WSEL of CNTL-S register)

0 0 +/- 3T

0 1 +/- 7T

1 0 +/- 13T

1 1 +/- 26T

FSMD1, FSMD0

Set the Frame Sync Detection mode

0 0 Pattern mode detect

0 1 Period mode detect

1 0 Compensation mode detect

1 1 Mixed mode detect (only 22T)

12. CNTL-H ($8DXX)

This register sets the Digital PLLs Processing Mode and Monitoring pin output Mode.

Bit

Identifier

7

6

RES8

-

5

4

3

2

1

0

-

-

DUMB3 DUMB2 DUMB1 DUMB0

RES8

PLCK Resolution when 2X speed

0 PLCK = VCO * 6

1 PLCK = VCO * 8

DUMB3, DUMB2, DUMB1, DUMB0

Set the Monitoring Pin Output Mode

0 Monitoring pin output disable

1 Monitoring pin output enable

- DUMB3 : DSVO, APDO

- DUMB2 : C4M

- DUMB1 : C16M

- DUMB0 : EFMFLAG, UDTFLAG, EFMZ, V34M, FSYNC, FLAG5 ~ FLAG1, /PBCK, FSDW,

ULKFS, /JIT

18

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