M2S56D20TP-10 View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2S56D20TP-10 Datasheet PDF : 36 Pages
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DDR SDRAM (Rev.0.0)
MITSUBISHI LSIs
Sep.'99 Preliminary
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
CLK
setting the mode register (MRS). The mode register stores these data
/CLK
until the next MRS command, which may be issued when both banks are /CS
in idle state. After tRSC from a MRS command, the DDR SDRAM is
/RAS
ready for new command.
/CAS
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/WE
BA0
0 0 0 0 0 DR 0 LTMODE BT
BL
BA1
A11-A0
V
Latency
Mode
CL
000
001
010
011
100
101
110
111
/CAS Latency
R
R
2
R
R
1.5
2.5
R
DLL
0
Reset
1
NO
YES
Burst
Length
BL
000
001
010
011
100
101
110
111
Burst
0
Type
1
BT= 0
R
2
4
8
R
R
R
R
BT= 1
R
2
4
8
R
R
R
R
Sequential
Interleaved
R: Reserved for Future Use
MITSUBISHI
ELECTRIC
13
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