M2V56S20TP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V56S20TP

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.1)

Single Data Rate

Feb.2000

MITSUBISHI LSIs

M2V56S20/ 30/ 40/ TP -6, -7, -8

256M Synchronous DRAM

[ Write Interrupted by Precharge ]

Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is

required from the last data to PRE command. During write recovery, data inputs must be masked by

DQM.

Write interrupted by Precharge (BL=4)

CLK

Command

A0-9,11-12

ACT

Xa

Write

Ya

PRE

ACT

tRP

Xa

A10

0

0

0

0

BA0-1

00

00

00

00

DQM

DQ

tWR

Da0 Da1

[ Write Interrupted by Burst Terminate ]

Burst terminate command can terminate burst write operation. In this case, the write recovery time is

not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.

Write interrupted by Terminate (BL=4)

CLK

Command

ACT

Write

TBST

Write

A0-9,11-12

Xa

Ya

Yb

A10

0

0

0

BA0-1

00

00

00

DQ

Da0 Da1

Db0 Db1 Db2 Db3

MITSUBISHI ELECTRIC

22

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