M2V56S20TP View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V56S20TP Datasheet PDF : 49 Pages
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SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits(max)
Organiz
ation 133
100 Unit Note
MHz
MHz
x4
90
Icc1
Operating Current
(1bank)
tCLK=min, tRC=min, BL=1
x8
90
x16
100
Icc2P Idle Standby Current tCLK=min, CKE≤VILmax
1.5
Icc2PS in Power Down Mode tCLK=∞, CKE≤VILmax
1
Icc2N
Idle Standby Current
tCLK=min, CKE≥VIHmin,
/CS≥ VIHmin
25
in Normal Mode
Icc2NS
tCLK=∞, CKE≥VIHmin
6
Icc3P Active Standby Current tCLK=min, CKE≤VILmax
5
Icc3PS in Power Down Mode tCLK=∞, CKE≤VILmax
4
Icc3N
tCLK=min, CKE≥VIHmin,
Active Standby Current /CS≥ VIHmin
30
in Normal Mode
Icc3NS
tCLK=∞, CKE≥VIHmin
15
Icc4
Burst Operating
Current
x4
110
tCLK=min, BL=4, gapless data x8
110
x16
120
Icc5 Auto-Refresh Current tCLK=min, tRFC=min
180
Icc6 Self-Refresh Current CKE≤0.2v
-6/-7/-8
3
80
80 mA 1
90
1 mA
2
1 mA
20 mA 2,3
6 mA 2,4
4 mA
5
4 mA
25 mA 3,5
15 mA 4,5
90
90 mA 5
100
170 mA
3 mA
Notes
1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are changed one time during 3xtCLK
4. input signals are stable
5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Test Conditions
VOH(DC) High-Level Output Voltage (DC) IOH=-2mA
Limits
Unit
Min. Max.
2.4
V
VOL(DC) Low-Level Output Voltage (DC) IOL= 2mA
0.4 V
IOZ
Off-state Output Current
Q floating Vo=0 ~ VddQ
-10
10 µA
II
Input Current
VIH=0 ~ VddQ+0.3V, other input pins=0V -10
10 µA
MITSUBISHI ELECTRIC
30
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