MC13109FB View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC13109FB Datasheet PDF : 28 Pages
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MC13109
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C)
Characteristic
Condition
Measure
Pin
Symbol
Min
PLL PIN INTERFACE
EN to Clk Setup Time
Data to Clk Setup Time
Hold Time
Recovery Time
Input Pulse Width
Input Rise and Fall Time
–
EN, Clk
tsuEC
200
–
Data, Clk
tsuDC
100
–
Data, Clk
th
90
–
EN, Clk
trec
90
–
EN, Clk
tw
100
–
Data
tr, tf
–
Clk
–
EN
–
MPU Interface Power–Up
Delay
90% of PLL Vref to
Data, Clk, EN
–
tpuMPU
–
PLL LOOP
Characteristic
Condition
Measure
Pin
Symbol
Min
2nd LO Frequency
–
“Tx VCO” Input Frequency Vin = 200 mVpp
LO2 In
fLO
–
LO2 Out
Tx VCO
ftxmax
–
Max
Unit
–
ns
–
ns
–
ns
–
ns
–
ns
9.0
µs
–
–
100
µs
Max
Unit
12
MHz
80
MHz
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL’s and MPU serial interface are
normally powered by the internal voltage regulator at the
“PLL Vref” pin. The “PLL Vref” pin is the output of a voltage
regulator which is powered from the “VCC Audio” power
supply pin. Therefore, the maximum input and output levels
for most PLL I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx
VCO) is the regulated voltage at the “PLL Vref” pin. The ESD
protection diodes on these pins are also connected to “PLL
Vref”. Internal level shift buffers are provided for the pins
(Data, Clk, EN, Clk Out) which connect directly to the
microprocessor. The maximum input and output levels for
these pins is VCC. Figure 9 shows a simplified schematic of
the PLL I/O pins.
Figure 9. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
VCC Audio PLL Vref
(2.0 to 5.5 V) (2.2 V)
VCC Audio
(2.0 to 5.5 V)
I/O
In
1.0 kΩ
Out
LO2 In, LO2 Out,
Rx PD, Tx PD and
Tx VCO Pins
2.0 µA
Data, Clk, and EN Pins
Clk Out Pin
Microprocessor Serial Interface
The “Data”, “Clk”, and “EN” pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The “Data” and “Clk” pins are used to load
data into the shift register. Figure 10 shows “Data” and “Clk”
pin timing. Data is clocked on positive clock transitions.
Figure 10. Data and Clock Timing Requirement
tr
tf
90%
Data,
10%
Clk, EN
50%
Data
tsuDC
th
50%
Clk
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 11 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 11. Enable Timing Requirement
50%
Clk
tsuEC
Last
Clock
50%
First
Clock
trec
50%
50%
EN
Previous Data Latched
16
MOTOROLA ANALOG IC DEVICE DATA
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