MPC8540(2004) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8540
(Rev.:2004)

PowerQUICC III™ Integrated Host Processor Reference Manual

Freescale Semiconductor 

Contents

Paragraph

Number

Title

Page

Number

6.11

6.11.1

6.11.2

6.11.3

6.11.4

6.12

6.12.1

6.12.2

6.12.3

6.12.4

6.12.4.1

6.12.4.2

6.12.5

6.12.5.1

6.12.5.2

6.12.5.3

6.12.5.4

6.12.5.5

6.12.5.6

6.13

6.13.1

6.13.1.1

6.13.1.2

6.13.1.3

6.13.2

6.13.3

6.13.4

6.14

6.14.1

6.15

6.15.1

6.15.2

6.15.3

6.15.4

L1 Cache Configuration Registers................................................................................. 6-30

L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 6-30

L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 6-31

L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 6-32

L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 6-33

MMU Registers.............................................................................................................. 6-34

Process ID Registers (PID0–PID2)............................................................................ 6-34

MMU Control and Status Register 0 (MMUCSR0) .................................................. 6-34

MMU Configuration Register (MMUCFG) .............................................................. 6-35

TLB Configuration Registers (TLBnCFG)................................................................ 6-35

TLB0 Configuration Register 0 (TLB0CFG) ........................................................ 6-35

TLB1 Configuration Register 1 (TLB1CFG) ........................................................ 6-36

MMU Assist Registers............................................................................................... 6-37

MAS Register 0 (MAS0) ....................................................................................... 6-37

MAS Register 1 (MAS1) ....................................................................................... 6-38

MAS Register 2 (MAS2) ....................................................................................... 6-39

MAS Register 3 (MAS3) ....................................................................................... 6-40

MAS Register 4 (MAS4) ....................................................................................... 6-40

MAS Register 6 (MAS6) ....................................................................................... 6-41

Debug Registers ............................................................................................................. 6-42

Debug Control Registers (DBCR0–DBCR2) ............................................................ 6-42

Debug Control Register 0 (DBCR0)...................................................................... 6-42

Debug Control Register 1 (DBCR1)...................................................................... 6-43

Debug Control Register 2 (DBCR2)...................................................................... 6-45

Debug Status Register (DBSR).................................................................................. 6-46

Instruction Address Compare Registers (IAC1–IAC2) ............................................. 6-47

Data Address Compare Registers (DAC1–DAC2).................................................... 6-48

Signal Processing and Embedded Floating-Point Status and

Control Register (SPEFSCR) .................................................................................... 6-48

Accumulator (ACC)................................................................................................... 6-50

Performance Monitor Registers (PMRs) ....................................................................... 6-51

Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-52

Local Control A Registers

(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3) ...................................................... 6-52

Local Control B Registers

(PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) ..................................................... 6-53

Performance Monitor Counter Registers

(PMC0–PMC3, UPMC0–UPMC3) ....................................................................... 6-54

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xi

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